1. Technical Field
The disclosed embodiments relate to the correction of the transfer function of a phase-to-digital (PDC) converter in an all digital phase-locked loop (ADPLL).
2. Background Information
Phase-locked loops are used in many applications, including use in local oscillators of cellular telephone receivers and transmitters. In the past, such phase-locked loops as employed in cellular telephones were generally implemented with analog circuitry. More recently, however, digital implementations of phase-locked loops have been employed. These phase-locked loops are often referred to as All-Digital Phase-Locked Loops (ADPLLs). There are several categories of ADPLL circuits including, for example, so-called Phase-to-Digital Converter PLLs (PDC ADPLLs) and so-called Time-to-Digital PLLs (TDC ADPLLs).
FIG. 1 (Prior Art) is a high level simplified conceptual circuit diagram of a TDC ADPLL 1. TDC ADPLL 1 involves a loop filter 2 that outputs a stream of digital tuning words. A Digitally Controlled Oscillator (DCO) 3 receives a digital tuning word and outputs a corresponding signal HCLK whose frequency is determined by the digital tuning word. A Time-to-Digital Converter (TDC) 4 receives the HCLK signal as well as a reference clock FREF and outputs a fractional part of a phase error word. The phase error word is indicative of a phase error between the FREF signal and the HCLK signal. An accumulator 5 outputs an integer portion of the phase error word. A summer 6 sums corresponding integer portions and fractional portions to output a stream of digital phase error words. The stream of digital phase error words is supplied to loop filter 2. When the loop is locked, the phase of HCLK is locked to the phase of the reference clock FREF. For additional information on a TDC ADPLL, see the article entitled “1.3 V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS”, IEEE Transactions on Circuits and Systems—II, Vol. 53, No. 3, March 2006, by Staszweski et al.
FIG. 2 (Prior Art) is a circuit diagram of TDC 4 of FIG. 1. TDC 4 includes a chain of inverters 7, an associated set of flip-flops 8, a decoder 9, and self-calibrating normalization circuitry 10-12. FIG. 3 (Prior Art) is a waveform diagram that illustrates the signals FREF and HCLK as they are supplied to the inputs of TDC 4. FIG. 4 (Prior Art) is a waveform diagram that illustrates the values D1-D10 that are output by the corresponding inverters along the chain of inverters 7. At a point in time indicated by the vertical dashed line 13 in the waveform diagram, the set of flip-flops 8 is clocked by the rising edge of the signal FREF. The values of the various inverters are then output in parallel as a word Q(1:10) to decoder 9. The word Q(1:10) contains information on the time separation between the rising edge of FREF and the rising and falling edges of HCLK. The word Q(1:10) is decoded by decoder 9 to output a six-bit falling time Δtf and a six-bit rising time value Δtr. The six-bit falling time value Δtf is indicative of the time between the falling edge of HCLK and the rising edge of FREF. The six-bit rising time value Δtr is indicative of the time between the rising edge HCLK and the rising edge of FREF. As indicated in FIG. 2, the values Δtf are, after being normalized by multiplier 12, the outputs OUT of the TDC. If the delays through the inverters of the inverter chain were to change due to variations in process, voltage and/or temperature, then the resulting values Δtr would also change and the phase-to-digital conversion gain would change. The TDC therefore self-calibrates to account for variations in inverter delay over changes in process, voltage and temperature (PVT). Blocks 10 and 11 generate values that are supplied to multiplier 12 to self-calibrate the stream of Δtr values.
FIG. 5 (Prior Art) is a simplified block diagram of one circuit topology 14 of a Phase-to-Digital Converter All-Digital Phase-locked Loop (PDC ADPLL). In one PDC ADPLL, the loop filter 15 is to receive signed numbers from the Phase-to-Digital Converter 16. The TDC ADPLL topology of FIG. 2, however, does not generate positive and negative values of Δtr values. Moreover, the period of the loop divider 17 output DIV_OUT in the PDC ADPLL may be many times (for example, a thousand times) longer than the period of HCLK depending on the value by which loop divider 17 divides. Providing a delay chain long enough to capture an entire high pulse of DIV_OUT may be unworkable and impractical. In addition, the technique employed in the TDC ADPLL of FIG. 2 involves supplying the DCO output signal HCLK into a chain of inverters. If the DCO output signal HCLK is of a high frequency such as 4 GHz, then the inverters of the delay chain that receive HCLK would be made to switch at a high frequency. If the inverters are complementary logic (CMOS) inverters, then the current consumption of the circuit would be undesirably high. Accordingly, the prior art technique of FIG. 2 is undesirable and cannot be effectively employed for self-calibration in a PDC ADPLL for multiple reasons.